A study of SEU-tolerant latches for the RD53A chip

International audienceThe RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process has been adopted in order to satisfy the high level of integration requirement. However, the SEU immunity should be carefully considered for a deep submicron process like the 65 nm. Indeed, the device dimensions are small and the capacitance of the storage nodes becomes very low. A chip prototype including different SEU tolerant structures was designed in a 65 nm technology. Several proton irradiation tests were carried out in order to estimate the SEU tolerance of the proposed structures and the level of improvement comparing with a standard architecture

Etude et mise en oeuvre de cellules résistantes aux radiations dans le cadre de l'évolution du détecteur à pixels d'Atlas technologie CMOS 65 nm

This study is inside an international collaboration context, RD53, which its goal is to provide to the scientific community an electronic front-end for the readout of the future pixel detector in 2022. The 65 nm technology chosen by the collaboration will have to be operational in a highly radioactive environment (10 MGray) for five years without maintenance operation.Two experimental approaches are described in this thesis: 1. Irradiation studies were carried out to estimate the dose tolerance (TID) of the 65 nm process to fix all essentials design rules for digital and analog cells implanted in the final circuit. Test vehicles (PCM) were defined for irradiation using an X-ray source (10 keV - 3 kW) to estimate dose effects. The results we obtained are summarized in the document. 2. In order to optimize the tolerance of memories to the SEE effects, several ASIC prototypes havebeen designed. These prototypes include different architectures for irradiation characterization. Several irradiation campaigns have been carried out using a heavy ion beam and a proton beam in order to a cross-section as accurate as possible.Cette étude s’inscrit dans le cadre d’une collaboration internationale, RD53, et qui vise à fournir à la communauté scientifique un ASIC « Front-End » de lecture du futur détecteur pixels courant 2022. La technologie 65 nm choisie par la communauté scientifique devra fonctionner dans un environnement extrêmement radioactif (10 MGray) pendant cinq ans d’exploitation sans maintenance possible.Deux approches expérimentales sont décrites dans ce mémoire : 1. Des études en irradiation ont été réalisées afin d'estimer la tolérance à la dose (TID) du process 65 nm pour fixer des règles de conception qui peuvent être respectées pour les cellules numériques et analogiques implantées dans le circuit final. Des véhicules de test (PCM) ont été définis pour être irradiés à l’aide d’une source de rayons X (10 keV – 3 kW) afin d'estimer les effets de dose. Les résultats obtenus sont synthétisés dans les chapitres concernés. 2. Dans le but d'optimiser l'immunité des points mémoires aux effets des SEU, plusieurs circuits prototypes ont été conçus. Ils incluent différentes architectures en vue d’être irradiées. Plusieurs campagnes d'irradiation ont été menées en utilisant un faisceau d'ions lourds et un faisceau de protons à dessein de comparer leur comportement et d’en extraire une cross-section la plus précise possible

Studies or rad-hard cells for the future ATLAS pixel detector in 65 nm CMOS technology

Cette étude s’inscrit dans le cadre d’une collaboration internationale, RD53, et qui vise à fournir à la communauté scientifique un ASIC « Front-End » de lecture du futur détecteur pixels courant 2022. La technologie 65 nm choisie par la communauté scientifique devra fonctionner dans un environnement extrêmement radioactif (10 MGray) pendant cinq ans d’exploitation sans maintenance possible.Deux approches expérimentales sont décrites dans ce mémoire : 1. Des études en irradiation ont été réalisées afin d'estimer la tolérance à la dose (TID) du process 65 nm pour fixer des règles de conception qui peuvent être respectées pour les cellules numériques et analogiques implantées dans le circuit final. Des véhicules de test (PCM) ont été définis pour être irradiés à l’aide d’une source de rayons X (10 keV – 3 kW) afin d'estimer les effets de dose. Les résultats obtenus sont synthétisés dans les chapitres concernés. 2. Dans le but d'optimiser l'immunité des points mémoires aux effets des SEU, plusieurs circuits prototypes ont été conçus. Ils incluent différentes architectures en vue d’être irradiées. Plusieurs campagnes d'irradiation ont été menées en utilisant un faisceau d'ions lourds et un faisceau de protons à dessein de comparer leur comportement et d’en extraire une cross-section la plus précise possible.This study is inside an international collaboration context, RD53, which its goal is to provide to the scientific community an electronic front-end for the readout of the future pixel detector in 2022. The 65 nm technology chosen by the collaboration will have to be operational in a highly radioactive environment (10 MGray) for five years without maintenance operation.Two experimental approaches are described in this thesis: 1. Irradiation studies were carried out to estimate the dose tolerance (TID) of the 65 nm process to fix all essentials design rules for digital and analog cells implanted in the final circuit. Test vehicles (PCM) were defined for irradiation using an X-ray source (10 keV - 3 kW) to estimate dose effects. The results we obtained are summarized in the document. 2. In order to optimize the tolerance of memories to the SEE effects, several ASIC prototypes havebeen designed. These prototypes include different architectures for irradiation characterization. Several irradiation campaigns have been carried out using a heavy ion beam and a proton beam in order to a cross-section as accurate as possible

Etude et mise en œuvre de cellules résistantes aux radiations dans le cadre de l'évolution du détecteur à pixels d'ATLAS en technologie CMOS 65 nm

The 65 nm CMOS technology is a promising technology for the pixel readout chips at HL-LHC in terms of high integration density. The RD53 collaboration was established to develop next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC, and requiring extreme rate and radiation tolerance. A first 65 nm demonstrator chip (RD53A) has been submitted during the summer 2017. The innermost parts of the new pixel detector will integrate a fluence of about 2.10$^{16}$ n/cm$^{2}$ (1 MeV neutron equivalent) and about 1 GRad Total Ionizing Dose (TID) for 10 years of exploitation. In this work, irradiation studies were done and are presented in order to estimate the TID tolerance of the 65 nm process, and fix some design rules to ensure good functionality in these aggressive operating conditions. Also , in order to optimize the immunity of latches against Single Event Upsets (SEU), various SEU-tolerant structures were designed in the 65 nm technology. This work presents these structures, the tests done at heavy ion beam facilities or under proton irradiations, and shows the level of improvement reached comparing to a standard latch architecture

RECOVERY OF DIFFERENTIATION/INTEGRATION COMPATIBILITY OF MESHLESS OPERATORS VIA LOCAL ADAPTATION OF THE POINT CLOUD IN THE CONTEXT OF NODAL INTEGRATION

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Monte Carlo simulation of SiPMs with GATE

International audienceSilicon photomultipliers (SiPMs) replace photomultiplier tubes (PMTs) for the detection of light in many applications, particularly in high energy physics and medical imaging. We describe a flexible implementation of a SiPM model for the GATE Monte Carlo simulation platform, which is based on the SiPM noise description proposed by Rosado and Hidalgo, and describe an easy and effective method to determine and instantiate the SiPM noise model with simple measurements. We also simulate the micro-cell Single Photon Time Resolution (SPTR) and describe its measurement

Monte Carlo simulation of a scintillation crystal read by a SiPM with GATE

International audienceSilicon photomultipliers (SiPMs) have recently emerged as a replacement for photomultiplier tubes (PMTs) for light detection in many applications, including high-energy physics and medical imaging. Recently, detailed Monte Carlo simulation of SiPMs has been implemented in GATE to quantify the impact of SiPM specifications on the linearity, energy and time resolution of a scintillation crystal read by a SiPM. In this paper, GATE simulations of a LYSO crystal coupled to a SiPM are compared to measurements. The energy spectra of the 241Am and 22Na radioactive sources are found to agree with less than 2% difference. The linearity of the SiPM response is duly affected by the SiPM saturation and, as seen above 511 keV with our configuration, it is slightly enhanced by the generation of crosstalk. Furthermore, with an over-voltage close to that recommended by the manufacturer, all sources of SiPM noise contribute about equally to the degradation of the energy resolution at low energies, which is downgraded by more than 15% at 60keV, but have less impact at higher energies. In addition, the GATE simulations show that crosstalk plays an important role on the time resolution of the installation

Single event effects testing of the RD53B chip

International audienceThe RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm$^{2}$ The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. Different SEE mitigation techniques based on the Triple Modular Redundancy (TMR) have been adopted for the critical information in the chip. Furthermore, the efficiency of this mitigation scheme has been evaluated for the RD53B chip with heavy ion beams in the CYCLONE facility and with a 480 MeV proton beam in TRIUMF facility. The purpose of this paper is to describe and explain all the SEE mitigation strategies used in the RD53B chip, to report and analyze the heavy ions and proton tests results and to estimate the expected Single Event Upset (SEU) rates at the HL-LHC

Physical Characterization of a Wireless Radiotracer Detection System Based on Pixelated Silicon for in Vivo Brain Studies in Freely Moving Rats

BLUPS for the four phenotypic traits studied. Each row corresponds to one individual